论文一种用于SARADC高能效高面效DAC是关于对写作SARADC论文范文与课题研究的大学硕士、相关本科毕业论文saradc论文开题报告范文和相关文献综述及职称论文参考文献资料下载有帮助。
摘 要 數模转换器（DAC）是逐次逼近型模数转换器（SAR ADC）能耗的重要来源之一. 为了降低DAC能耗,提出一种高能效高面效DAC结构,该结构包含四个子DAC. 在DAC转换过程中,通过采用附加步技术,使同边的两个子DAC结合产生所需要的DAC输出电压. 而且,子DAC结合可使所需的单位电容数量减少,能耗降低. 仿真结果表明,相比于传统的DAC结构,文中提出的DAC结构可降低99.89%的能耗,节省96.875%的单位电容数量.
关键词 高能效；高面效；逐次逼近型模数转换器；子DAC结合；附加步
In successive approximation register （SAR） analogue-to-digital converters （ADCs）, DAC consumes a significant part of the total power consumption [1]. Recently, several energy-efficient techniques have been developed to improve the power efficiency of DAC [1-10]. Compared to conventional technique, Split capacitor [1], Set-and-down [2], Vcm-based [3], Tri-level [4], Mohsen [5], VMS [6], Sanyal [7], Asymmetric monotonic [8], HCS [9], Liang [10] reduced the energy consumption by 37.48%, 81.26%, 87.52%, 96.89%, 97.26%, 97.66%, 98.40%, 98.50%, 98.84% and 99.40%, respectively. In this paper, a more energy-efficient and area-efficient DAC is presented which can achieve the reduction of 99.89% in the energy consumption of the DAC.
1 The proposed DAC
1.1 The structure of the proposed DAC
The structure of the proposed DAC for SAR ADC is shown in Fig.1. The DAC consists of four sub-DACs, sub-DAC（p0）, sub-DAC（p1）, sub-DAC（n0） and sub-DAC（n1）, with the first two combined into one sub-DAC combination and the latter two into another one. Each sub-DAC has M（M等于N/2, if N is even； M等于（N+1）/2, if N is odd） sub-capacitor sections and the number in each box is the total capacitance of the sub-capacitor section. All the top plates of the sub-capacitor sections connecting serially through additional switches join to sampling port, and their bottom plates connect serially.
1.2 The application of extra-step in sub-DAC combination
The main idea of this paper stems from the method of using an extra-step to generate an extra voltage on the DAC, and combining sub-DACs （as shown in Fig.1.） to get a finer voltage. It can save more energy and reduce more areas for DAC than that by conventional techniques.
Fig.2 The application of extra-step in sub-DAC combination
As shown in Fig.2, in “Before extra-step”, the sub-DAC（p0） and sub-DAC（p1） have the same voltage as they use the same reference voltage. In “Extra-step”, the voltage of sub-DAC（p1） increases by Vref/4 through a shift in the reference voltage of the second capacitor from gnd to Vcm； the voltage of sub-DAC（p1） decreases by Vref/4 through a shift in the reference voltage of the first capacitor from Vcm to gnd. In “After extra-step”, the switches between the second capacitor and reference voltage in both of the sub-DAC（p0） and sub-DAC（p1） are opened, while the switch Sp between sub-DAC（p0） and sub-DAC（p1） is closed. In this way, a finer voltage of sub-DAC（p0） and sub-DAC（p1）, Vref/8 or-Vref/8, is achieved through the application of extra-step technique.
总结:本论文可用于SARADC论文范文参考下载，SARADC相关论文写作参考研究。
参考文献：
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